1. Field of the Invention
The present invention relates to a debugging apparatus and method, and more particularly, to a debugging apparatus and method that is capable of recognizing a data conversion in a specific memory location by observing a change and flow of specific data memory location and performing a debugging process.
2. Description of the Background Art
In general, a debugging apparatus for detecting an error generated in a program input to a microprocessor includes a host computer and a microprocessor unit (MPU).
In the debugging apparatus, when the host computer selects a specific address of program memory in the MPU as a break point, the MPU monitors the processor while the processor is being operated and when the specific address of the program memory accessed is identical to the memory address selected as the break point, the MPU recognizes the selected memory address as a break point and discontinues the operation of the processor and the host computer observes the flow of the program and performs a debugging process.
FIG. 1 is a schematic block diagram of the debugging apparatus in accordance with the conventional art.
As shown in FIG. 1, the debugging apparatus includes: a host computer 1 for selecting a specific address of a memory as a break point and performing a debugging process; a debugger controller 2 for receiving a control command from the host computer I and outputting a break enable signal and a break point address; a processor 4 operating upon receiving a control signal from the debugger controller 2; a program memory 5 for storing a program of the processor 4; a data memory 6 for storing data of the processor 4; and a break point sensing unit 3 for receiving the break enable signal and the break point address from the debugger controller 2, observing an address of the program memory 5 being executed in the processor 4, and recognizing the address as a break point and outputting a break signal to the debugger controller 2.
The operation of the debugging apparatus constructed as described above will now be explained.
When the processor is switched to a debugging mode, the host computer 1 outputs a processor stop signal and a break point address to the debugger controller 2 for debugging.
The debugger controller 2 outputs a stop signal to the processor 4 to suspend the processor 4 operation and outputs a break point address and a break enable signal to the break point sensing unit 3.
When the break point sensing unit 3 stores a program address in the program memory at which the processor 4 is to suspend operation, or a break point address, the host computer 1 operates the processor 4 in the order of programs stored in the program memory 5.
While the processor 4 is operated, the break point sensing unit 3 observes a program address output to the processor 4.
Subsequently, when the break point sensing unit 3 detects an accessed address of the program memory 5 as that of the stored program address, a break signal is output to the debugger controller 2.
The debugger controller 2 suspends the operation of the processor 4 according to the break signal received from the break point sensing unit 3 and shifts debugging control to the host computer 1 so that the host computer 1 may perform a debugging operation.
However, in the debugging method, since an operation is determined by an address of a specific program memory among the sequential programs, it is not possible to recognize a data flow according to a data memory. Thus, in case where an error occurs by data, much time and expense is taken for debugging.
In addition, when creating a program, since the state of data is not recognized, an error may occur in the allocation of data memory. In addition, if the wrong data is read in a calculating process, an erroneous result is output and may cause a system malfunction.